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CY7C185A
8K x 8 Static RAM
Features
* High speed -- 20 ns * CMOS for optimum speed/power * Low active power -- 743 mW * Low standby Power -- 220 mW * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2 and OE features * Automatic power-down when deselected three-state drivers. The device has an automatic power-down feature (CE1), reducing the power consumption by over 70% when deselected. The CY7C185A is in the standard 300-mil-wide DIP package and leadless chip carrier. Writing to the device is accomplished when the Chip Enable one (CE1) and Write Enable (WE) inputs are both LOW, and the Chip Enable two (CE2) input is HIGH. Data on the eight I/O pins (I/O 0 through I/O 7) is written into the memory location specified on the address pins (A0 through A12). Reading the device is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW, while taking Write Enable (WE) and Chip Enable two (CE 2) HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the I/O pins. The I/O pins remain in a high-impedance state when Chip Enable one (CE1) or Output Enable (OE) is HIGH, or Write Enable (WE) or Chip Enable two (CE2) is LOW. A die coat is used to ensure alpha immunity.
Functional Description
The CY7C185A is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and
Logic Block Diagram
Pin Configurations
DIP Top View
NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
LCC Top View
3 2 1 28 27 4 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 18 1314151617 I/O2 GND I/O3 I/O4 I/O5 C185A-3 A6 A5 A4 VCC WE NC A7 A8 A9 A10 A11 A12 I/O0 I/O1 CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6
I/O0 INPUT BUFFER I/O1 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER I/O2 I/O3 I/O4 I/O5 I/O6 CE1 CE2 WE OE COLUMN DECODER
POWER DOWN
8K x 8 ARRA Y
SENSE AMPS
C185A-2
I/O7
A10
A11
A12
A0
A9
C185A-1
Selection Guide[1]
7C185A-20 Maximum Access Time (ns) Maximum Operating Current (mA) Military Maximum Standby Current (mA) Military
Note: 1. For commercial specifications, see the CY7C185 data sheet.
7C185A-25 25 125 40/20
7C185A-35 35 125 30/20
7C185A-45 45 125 30/20
20 135 40/20
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 October 4, 1999
CY7C185A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied .............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] .....................................................-0.5V to +7.0V DC Input Voltage[2] ................................................. -0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Military
[4]
Ambient Temperature[3] -55C to +125C
VCC 5V 10%
Electrical Characteristics Over the Operating Range[4]
7C185A-20 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current Automatic CE1 Power-Down Current Automatic CE1 Power-Down Current
[5] [2]
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA
Min. 2.4
Max. 0.4
Unit V V V V A A mA mA mA mA
2.2 -0.5 GND VI VCC GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max. IOUT = 0 mA Max. V CC, CE1 VIH, Min. Duty Cycle = 100% Max. V CC, CE1 VCC -0.3V VIN VCC -0.3Vor VIN 0.3V Military Military Military -10 -10
VCC 0.8 +10 +10 -300 135 40 20
VCC Operating Supply Current
Electrical Characteristics Over the Operating Range[4] (continued)
7C185A-25 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[5] VCC Operating Supply Current Automatic CE1 Power-Down Current Automatic CE1 Power-Down Current
[2]
7C185A-35, 45 Min. 2.4 Max. 0.4 2.2 -0.5 -10 -10 VCC 0.8 +10 +10 -300 125 30 20 Unit V V V V A A mA mA mA mA
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA
Min. 2.4
Max. 0.4
2.2 -0.5 GND VI VCC GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Max. VCC, CE1 VIH, Min. Duty Cycle=100% Military Military -10 -10
VCC 0.8 +10 +10 -300 125 40 20
Max. VCC, CE1 VCC -0.3V Military VIN VCC -0.3Vor VIN 0.3V
Notes: 2. VIL (min.) = - 3.0V for pulse durations less than 30 ns. 3. TA is the case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
CY7C185A
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
Note: 6. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255
C185A-4
R1 481 ALL INPUT PULSES 3.0V 10% GND 5 ns 90% 90% 10% 5 ns
C185A-5
(a)
Equivalent to: THEVENIN EQUIVALENT 167 OUTPUT 1.73V
(b)
3
CY7C185A
Switching Characteristics Over the Operating Range[7]
7C185A-20 Parameter READ CYCLE tRC tAA tOHA tACE1 tACE2 tDOE tLZOE tHZOE tLZCE1 tLZCE2 tHZCE tPU tPD tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z
[8]
7C185A-25 Min. Max.
7C185A-35 Min. Max.
7C185A-45 Min. Max. Unit
Description
Min.
Max.
20 20 3 20 20 10 3 8 5 3
[8, 9]
25 25 3 25 25 12 3 10 5 3 8 10 0 20 20
35 35 3 35 35 15 3 12 5 3 15 0 20
45 45 3 45 30 20 3 15 5 3 15 0 25
ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW to Low Z[9] CE2 HIGH to Low Z CE1 HIGH to High Z CE2 LOW to High Z
CE1 LOW to Power-Up CE1 HIGH to Power-Down
[10]
0
WRITE CYCLE
Write Cycle Time CE1 LOW to Write End CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[8]
20 15 15 15 0 0 15 10 0 3 7
20 20 20 20 0 0 15 10 0 5 7
25 25 25 25 0 0 20 15 0 5 10
40 30 30 30 0 0 20 15 0 5 15
ns ns ns ns ns ns ns ns ns ns ns
Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load capacitance. 8. t HZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 10. Device is continuously selected. OE, CE = VIL. CE2 = VIH.
4
CY7C185A
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C185A-6
Read Cycle No. 2[11, 12]
tRC CE1
CE2 tACE OE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB
C185A-7
HIGH IMPEDANCE
DATA OUT
ICC
Write Cycle No. 1 (WE Controlled)[13, 14]
tWC ADDRESS tSCE1 CE1
CE2 tSCE2 OE WE tSA tAW tPWE tHA
tSD DATA IN tHZOE HIGH IMPEDANCE DATA I/O DATA UNDEFINED DATAIN VALID
tHD
tLZWE
C185A-8
Notes: 11. Address valid prior to or coincident with CE transition LOW. 12. WE is HIGH for read cycle. 13. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 14. Data I/O is high impedance if OE = VIH.
5
CY7C185A
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[13, 14, 15]
tWC ADDRESS tSCE1 CE1 tSA CE2 tSCE2 tAW tPWE WE tSD DATA IN DATAIN VALID HIGH IMPEDANCE
C185A-9
tHA
tHD
DATA I/O
Note: 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
6
CY7C185A
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA)
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 I SB 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 6.0 I CC NORMALIZED I CC, I SB NORMALIZED I CC, ISB 1.2 1.0 0.8 0.6 0.4 0.2
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) VCC =5.0V TA =25C
I CC
ISB
VCC =5.0V VIN =5.0V
0.0 -55
25 125 AMBIENT TEMPERATURE (C)
OUTPUT SINK CURRENT (mA)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED tAA 1.3 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0
C185A-10
VCC =5.0V TA =25C
VCC =5.0V 0.8 0.6 -55
25
125
SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO 2.5 DELTA t AA (ns) 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0
AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC
OUTPUT VOLTAGE (V)
NORMALIZED I CC vs. CYCLE TIME VCC =5.0V TA =25C VCC =0.5V 1.00
25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC =4.5V TA =25C
0.75
600
800 1000
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
C185A-11
7
CY7C185A
Truth Table
CE1 CE2 WE OE H X L L L X L H H H X X H L H X X L X H Input/Output High Z High Z Data Out Data In High Z Mode Deselect/ Power-Down Deselect Read Write Deselect
Address Designators
Address Name A4 A5 A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 Address Function X3 X4 X5 X6 X7 Y1 Y4 Y3 Y0 Y2 X0 X1 Pin Number 2 3 4 5 6 7 8 9 10 21 23 24
Ordering Information
Speed (ns) 20 25 35 45 Ordering Code CY7C185A-20DMB CY7C185A-25DMB CY7C185A-35DMB CY7C185A-45DMB Package Name D22 D22 D22 D22 Package Type 28-Lead (300-Mil) CerDIP 28-Lead (300-Mil) CerDIP 28-Lead (300-Mil) CerDIP 28-Lead (300-Mil) CerDIP Operating Range Military Military Military Military
8
CY7C185A
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL Max. IIX IOZ IOS ICC ISB1 ISB2 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tRC tAA tOHA tACE1 tACE2 tDOE WRITE CYCLE tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Switching Characteristics
Parameter READ CYCLE 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Subgroups
Document #: 38-00114-C
9
CY7C185A
Package Diagram
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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